1. Field of the Invention
The present invention relates to a semiconductor memory device, especially relates to an improved decoder circuit used for a semiconductor memory device including non-volatile memory cells such as an EPROM and EEPROM requiring high voltage in a writing mode (programming mode) or erasing mode.
2. Description of the Related Art
Japanese Unexamined Patent Publication (Kokai) No. 61-45496 is known as a prior art of the invention of the present application.
The circuit construction and operation of the prior art will be explained hereunder with reference to FIG. 3.
In a decoder, a source voltage V.sub.PPI may be switched internally to two voltage levels i.e., a low voltage of about 5 V (referred to as V.sub.cc hereinafter) used in a reading mode and a high voltage of about 12.5 V (referred to as V.sub.PP hereinafter) used in a writing mode.
The decoder is provided with an N channel depletion type MOS transistor T.sub.1, N channel enhancement type MOS transistors T.sub.2 to T.sub.5 and T.sub.7, and a P channel enhancement type MOS transistor T.sub.6.
The transistors T.sub.1 to T.sub.5 constitute a NAND gate circuit (D).
An output N.sub.1 from output terminal N.sub.1 drives a CMOS inverter (IV) consisting of transistors T.sub.6 and T.sub.7.
An output of the CMOS inverter (IV) connects to a word line (WL).
A memory cell transistor MC is provided at each cross point of the word line (WL) and bit lines BL.sub.0, BL.sub.1, BL.sub.2 . . . .
Input address signals a to d are applied to the gates of the driving transistors T.sub.2 to T.sub.5 , respectively.
In a stable condition, these input address signals selectively show either the V.sub.cc level (logic "1") or V.sub.ss level (logic "0", usually showing the ground level, i.e., 0 V).
When all the voltage levels of the input address signals a to d are V.sub.cc , the node N.sub.1 (output of the decoder circuit) is reduced nearly to V.sub.ss, i.e., 0 V, regardless of whether the decoder source voltage V.sub.PPI is V.sub.cc or V.sub.PP.
Thus, the node N.sub.2, i.e., the output voltage of the inverter is increased to V.sub.PPI.
If one or more of the input address signals a to d is V.sub.ss, the output N.sub.1 of the decoder circuit (DEC) is increased to V.sub.PPI.
Thus, the output of the inverter N.sub.2 is reduced to V.sub.ss, i.e., 0 V.
Here, the input address signals a to d are given from, for example, the outputs of an address buffer circuit in which the address signals applied externally thereto are subjected to a waveform shaping operation inside the chip.
A problem arises in the operation of the NAND gate circuit (D) of the decoder circuit (DEC) (as shown in FIG. 4(a)).
FIG. 4(b) shows a load curve of the decoder circuit and the output characteristic curves of the transistors T.sub.2 to T.sub.5.
Lines .circle. and .circle. show the load curves indicating the characteristics of the depletion type transistor T.sub.1.
Line .circle. shows the load curve of the transistor T.sub.1 when V.sub.PPI is V.sub.cc, i.e., the reading mode, while line .circle. the load curve of the transistor T.sub.1 when V.sub.PPI is V.sub.PP i.e., the writing mode.
Line .circle. on the other hand, shows the output characteristic curve of the driving transistors T.sub.2 to T.sub.5, wherein the input V.sub.IN is shown as an input to which every input to each driving transistor of the driver circuit (D) is concentrated.
Each curve shows the output characteristics curve when the input V.sub.IN is varied from 0 V to 5 V.
Generally speaking, in such a decoder circuit, when the decoder source (V.sub.PPI), to which a different voltage in selectively applied, is V.sub.PP in the writing mode, the inverter, arranged down stream of the load means T.sub.1, will frequently be erroneously operated unless the output voltage V.sub.OUT at the output N.sub.1 of the decoder circuit (DEC) is reduced to nearly 0 V when the output V.sub.OUT is a low level.
Therefore, as apparent from the load curve .circle. shown in FIG. 4(b), in order to reduce the voltage of the output V.sub.OUT of the decoder circuit (DEC) at the node N.sub.1 absolutely to V.sub.ss, i.e., 0 V, transistors having a high driving performance, i.e., sufficiently large mutual conductance (gm), should be used for the transistors of T.sub.2 to T.sub.5.
The input and output characteristics curve of the decoder circuit (DEC) in the writing mode is shown in FIG. 4(d).
As seen, the output V.sub.OUT is V.sub.PP when the voltage V.sub.IN is below 1 V, while the output V.sub.OUT is reduced to nearly V.sub.ss when the voltage V.sub.IN exceeds 2.0 V preferably exceeds 2.5 V.
This means that the output V.sub.OUT of the decoder circuit (DEC) is reversed when the input voltage V.sub.IN is at around 2.5 V.
The input voltage V.sub.IN by which the output logic level of the NAND gate circuit of the decoder circuit (DEC) is reversed is called the threshold voltage of the NAND gate circuit.
The common sense among, persons engaged in design of the decoder circuits, is to design the input voltage (the threshold voltage of the NAND gate circuit) in the writing mode at around half of the source voltage.
Accordingly, supposing that V.sub.cc is set at 5 V, in order to give the input-output characteristics as shown in FIG. 4(d), to the decoder circuit (DEC), it is suitable to design the input voltage of the circuit (the threshold voltage of the NAND gate circuit) as V.sub.cc /2, i e., at around 2.5 V.
However, in the reading mode, in which the V.sub.PPI is V.sub.cc, the transistor T.sub.1 may not have as high performance as indicated by the load curve .circle. in FIG. 4(b).
Therefore, as shown by the input-output characteristics curve .circle. in FIG. 4(c), when the input voltage V.sub.IN is less than 1 V, the output voltage V.sub.OUT becomes V.sub.cc, while when the input voltage V.sub.IN exceeds 1.5 V, the output voltage V.sub.OUT becomes V.sub.ss, to make the threshold voltage thereof remarkably lower to 1.0 to 1.5 V.
This means that, when noise is added to an input signal, especially to an input signal having 0 V, this decoder circuit (DEC) may operate erroneously.
Thus, this circuit is weak against noise.
Note that, since the threshold voltage is low in the writing mode, the problem arises that when an output of an address buffer is increased by about 1.5 V from V.sub.ss due to noise, the output N.sub.2 of the inverter is turned to V.sub.cc due to the input N.sub.1 of the inverter being reduced to around 0 V, instead of the output N.sub.2 being naturally at V.sub.ss.
In a non-volatile semiconductor memory device such as an EPROM, after a writing operation is carried out, only a reading operation may be carried out until an erasing operation is effected, although erroneous operations easily occur in the reading mode because the threshold voltage level of the NAND gate circuit is extremely low.
Generally speaking, in a semiconductor device, for example, a buffer circuit, the internal ground potential in a chip will be varied due to the variation of the output thereof, so a differential potential will be created between the internal ground potential and an external ground potential in the chip.
Thus, when an address signal having an external ground potential as a reference potential is applied to a chip, the intended potential level of the address signal will be varied when the potential thereof is discriminated with reference to the internal ground potential of the chip.
Therefore, an abnormal situation used to frequently occur, in which the output voltage of the buffer circuit was increased from V.sub.ss instead of being naturally or the output voltage thereof was decreased from V.sub.cc instead of being naturally V.sub.cc.
One example of this problem will be explained in detail with reference to FIG. 5.
As shown in FIG. 5, an IC package 1 is provided with an IC chip 2, a V.sub.cc terminal 4, a V.sub.ss terminal 3, an input terminal 5, and an output terminal 6.
A load capacitance 7 is connected to the output terminal 6 of the package 1.
An electric source 8 providing a voltage of V.sub.cc and a signal source 9 connected to the input terminal 5 are also provided.
When the output voltage is switched from 5 V to 0 V, a discharge current from the load capacity 7 flows into the external ground terminal 3, which has a level of V.sub.ss, through wires and transistors provided in the chip and further a chip ground, i.e., the internal ground potential, having a level of V.sub.ss ', although in this situation, the level of the V.sub.ss ' in the chip 2 will increase due to an inductance element inside the chip.
Thus, the level of V.sub.ss ' in the chip 2 is sometimes instantly increased by a certain amount of voltage, for example, 2 V, instead of the level of V.sub.ss ' being naturally at 0 V.
On the other hand, assume the package is designed so that the input voltage from the signal source 9 is set at 3 V, the chip can discriminate the input signal as the "H" level when the input signal has a voltage exceeding 2 V, and the chip can discriminate it as the "L" level when the input signal has a voltage below 1 V.
In a package as explained above, when signal having a voltage of 3 V, is input, it will be discriminated as the "H" level in a normal condition.
However, when the level of V.sub.ss ' of the chip 2 is increased at 2 V even instantly as mentioned above, the signal input into the chip 2 will be discriminated as an input signal of 1 V.
Accordingly, it is ideal for the input characteristic of the decoder circuit that the threshold voltage be set at around V.sub.cc /2, i.e., at around 2.5 V, so that the decoder circuit can have a sufficient noise immunity even for an increment of the input voltage from V.sub.ss or decrement thereof from V.sub.cc due to noise applied thereto.
In a semiconductor memory device having a conventional decoder circuit as mentioned above, when the decoder erroneously operates, erroneous information is transferred to a memory cell array and finally a mistaken determination is made from the memory.
The reason for them will be explained with reference to FIGS. 6 to 9.
Generally speaking, as shown in FIG. 6, address signal inputs externally provided are applied to the input terminal of a buffer circuit with a waveform as shown in FIG. 6(a), are subjected to a waveform shaping operation, and are output to the input terminals of the decoder circuit with a waveform as shown in FIG. 6(b).
In this situation, suppose that when a noise Y is added to the address signal as shown in FIG. 6(a), the output signal of the address buffer inherently has the abnormal signal portion X and X' in response to the noise portion Y as shown in FIG. 6(b).
When the output signal of the address buffer including such an abnormal signal portion X is input to the decoder circuit, the decoder will erroneously operate depending upon the level of the abnormal signal portion and the level of the threshold set for the decoder circuit.
If the level of the abnormal signal portion is higher or lower than the threshold level set for the decoder circuit, the decoder circuit will erroneously operate and output an erroneous signal information Z to the word line WL as shown in FIG. 6(c).
More specifically, when the decoder circuit is set that, as shown in FIG. 7, the outputs of the address buffer having the "H" level are applied to the gates a, b, and c and the output having the "L" level is applied to the gate d of the decoder circuit (DEC), the input threshold voltage is set at 1.5 V.
Accordingly, in this situation, the output V.sub.OUT at the node N.sub.1 of the decoder circuit is at the "H" level and thus the output at the node N.sub.2 of the inverter is at the "L" level, as shown in FIG. 7.
Suppose that when an abnormal signal portion X having a level exceeding 1.5 V is instantly applied to the input terminal d, the level of the output V.sub.OUT of the decoder circuit is instantly switched to the "L" level instead of being the "H" level naturally, whereby the level of the output of the inverter is also instantly switched to the "H" level instead of being the "L" level naturally.
Therefore, in this situation, the word line WL connected to this decoder is a non-selected word line and thereby the signal level thereof inherently is "L", although the level of the word line will be increased from the level of 0 V to form an abnormal signal portion z as shown in FIG. 6(c) so as to mistakenly read or write information from or into a certain memory cell.
When the duration of such an abnormal signal portion is remarkably short, such a signal does not affect the circuit arranged downstream of the circuit concerned so much, although, when the duration is relatively long, it can affect it.
In a memory cell array used in a semiconductor memory device, a plurality of pairs of a resister and capacitor are serially arranged and an equivalent circuit thereof can be represented in a figure shown in FIG. 8.
The signal output from the inverter, including an abnormal signal level, will be delayed and the duration of the abnormal signal portion will be prolonged due to the plurality of time constants caused by CR.
When such a prolonged signal portion P is output to the sense amplifier, the erroneous data portion P will be read with a threshold level V.sub.L for a period t, as shown in FIG. 9.
Note that, when such erroneous information is created due to noise in the signals, it cannot easily be corrected in the successive circuit arranged downstream of the circuit where the erroneous operation took place.
To avoid such erroneous operation of not only the decoder circuit but also the semiconductor memory device, it has been proposed to construct an address buffer circuit so as not to respond to noise so sharply, but it is very difficult to prevent such problems completely by such a method.